1. Field of the Invention
The present invention relates to variable delay lines for adjusting the timing of high speed signal transmission between individual components of a computer, etc.
2. Description of the Prior Art
There are three types of variable delay lines; namely, (1) the semiconductor type which employs a semiconductor element; (2) the fixed type which makes use of fixed taps from the signal line which is opposed to the ground line; and (3) the sliding type which uses a sliding tap provided for the signal line which is opposed to the ground line.
The variable delay lines of the semiconductor type include a programmable delay line semiconductor element and an output buffer semiconductor element mounted on a circuit board within a package such that the amount of delay is changed by a driving power or controller.
As FIG. 8 shows, the variable delay lines of the fixed type include a ground line 1 and a signal line 2 opposed to the ground line 1 within a package which has an input terminal 1' to which an end of the signal line 2 is connected, intermediate tap terminals 2', 3', 4', 5', and 6', a ground terminal 7' to which the ground line 1 is connected, and an output terminal 8' to which the other end of the signal line 2 is connected. By selecting an intermediate tap terminal, it is possible to change the amount of delay.
As FIG. 9 shows, the variable delay lines of the sliding type include a ground line 3 and a signal line 4 opposed to the ground line 3 within a package, a signal input line 5 provided along the signal line 4, a sliding tap 6 across the signal line 4 and the input line 5, an input terminal 7 to which an end of the input line 5 is connected, an output terminal 8 to which an end of the signal line 4 is connected, and a ground terminal 9 to which the ground line 3 is connected. By moving the sliding tap 6 it is possible to change the amount of delay.
However, the variable delay lines of the semiconductor type not only require a driving power supply, complex circuitry, and a driving controller for controlling the drive, making them expensive as a whole but also have poor frequency characteristics because of the used semiconductor.
The variable delay lines of the fixed type employ one of the several intermediate taps so that there are many mismatching elements, providing poor frequency characteristics. For example, when the intermediate tap 4' is employed in FIG. 8, an element 10 consisting of the intermediate taps 2' and 3' and an element 11 consisting of the intermediate taps 5' and 6' part of the ground line 1, and part of the signal line 2 become mismatching, and their floating capacity and inductance provide poor characteristics.
The variable delay lines of the sliding type also bring about many mismatching elements, providing poor frequency characteristics. For example, the tap position in FIG. 9 is used, an element 12 consisting of part of the input line 5 and an element 13 consisting of part of the signal line 4 and part of the ground line 3 become mismatching, and their floating capacity and inductance provide poor frequency characteristics. In addition, it is difficult to know accurately the position of the sliding tap 6 and thus the amount of delay.